Floating Point ALU Simulation Using VHDL: A Survey

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S.K.Patil, S. N. Magdum, Nikita Gaikwad, Neha Hattalli, Anil Patil


VHDL environment is implemented for floating point arithmetic and logic unit design using pipelining; the novelty in the pipelining ALU design offers a high-performance ALU to simultaneously execute several instructions. Four arithmetic modules, addition, subtraction, multiplication and division, are combined in the top-down design approach to form a floating point ALU unit. In order to select a specific operation, each module is divided into sub-modules with two selection bits combined. Each module is mutually independent. In the Xilinx12.1i programmed, the modules are realized and tested by VHDL simulation.

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